Test Pattern Generation Based on Predicted Signal Integrity Loss through Reduced Order Interconnect Model

At higher operating (GHz) frequency the interconnect wire does not behave like a simple metallic resistance but as a transmission line. This being the main reason for signal integrity losses in high frequency interconnect line. Signal Integrity (SI) losses in the interconnect wires are the disturbances coming out of their distributed nature of parasitic capacitances, resistances and inductances at high frequency operation. These SI losses are further aggravated if multiple interconnect lines couple energy from or to each other. In the paper two interconnect lines, as per maximal aggressor fault model [9], have been considered where the aggressor line is assumed to couple energy to the victim line only, based on which the cross-talk model of an aggressor and a victim line has been developed using ABCD two-port network model. After the model order reduction by Pade-approximation various signal integrity losses, such as delay, overshoot, undershoot or glitch etc., for a given set of applied input transitions, are estimated numerically and verified through experimental PSPICE simulation. Based on the above prediction of SI losses the applied input transitions can be identified as potential test patterns that are believed to excite the SI faults. In order to simplify the crosstalk model computation only the capacitive coupling is considered here because, inductive coupling will contribute more significantly only if the operating frequency is higher than several GHz.